High-speed BiCMOS technology with a buried twin well structure
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I. Masuda | A. Watanabe | T. Ikeda | K. Ogiue | M. Odaka | N. Tamba | Y. Nishio | T. Ikeda | A. Watanabe | Y. Nishio | I. Masuda | N. Tamba | M. Odaka | K. Ogiue
[1] F. Walczyk,et al. A merged CMOS/bipolar VLSI process , 1983, 1983 International Electron Devices Meeting.
[2] T. Ikeda,et al. High speed BiCMOS VLSI technology with buried twin well structure , 1985, 1985 International Electron Devices Meeting.