Tutorial: Delay Fault Models and Coverage

Fazlures that cause logic circuits to malfunction at the desared clock rate and thus violate tlming specificattons are currently receavzng much attentzon. Such failures are modeled as delay faults. They facilitate delay testang. The use of delay fault models in VLSI test generatzon zs uery likely to gam rndustry acceptance in the near future. In thzs paper, we review delay fault models. discuss thew classificatzons and examine fault coverage metracs that have been proposed in the recent literature. A compari- son between delay fault models, namely, gate delay, tran- sition, path delay, line delay and segment delay faults, shows thew benefits and limitations. Various classafica- tions of the path delay fault model, that have receaved the most attention in recent years, are revzewed. We believe an understanding of delay fault models is essential in to- day's VLSI design and Lest environment.

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