Low-glitch, high-speed charge-pump circuit for spur minimisation
暂无分享,去创建一个
For spur reduction in RF frequency synthesisers, a simple and effective charge-pump circuit is proposed. A prototype frequency synthesiser fabricated on a 0.13 ?m CMOS process, achieves -71.32 dBc at 8.184 MHz offset from a 1.571 GHz carrier with just a second-order loop filter. When the spur level is converted to the input phase error of the PFD, it equals 0.0026 rad.
[1] Young-Shig Choi,et al. Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[2] José Silva-Martínez,et al. Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[3] Shin-Il Lim,et al. Charge pump with perfect current matching characteristics in phase-locked loops , 2000 .