The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter

An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 /spl mu/m CMOS process. The core area occupies 1450 /spl mu/m/spl times/1100 /spl mu/m. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage.

[1]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[2]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[3]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[4]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[5]  Michiel Steyaert,et al.  Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages , 1994, IEEE J. Solid State Circuits.

[6]  Bang-Sup Song,et al.  A 10-b 20-Msample/s low-power CMOS ADC , 1995, IEEE J. Solid State Circuits.

[7]  Paul R. Gray,et al.  A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 /spl mu/m CMOS , 1996 .

[8]  D. J. Allstot,et al.  Small-signal analysis and minimum settling time design of a one-stage folded-cascode CMOS operational amplifier , 1991 .

[9]  Michel Declercq,et al.  A high-efficiency CMOS voltage doubler , 1998, IEEE J. Solid State Circuits.

[10]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[11]  Ramesh Harjani,et al.  Dynamic amplifiers: settling, slewing & power issues , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[12]  Hae-Seung Lee.  A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC , 1994 .

[13]  P.G.A. Jespers,et al.  A CMOS 13-b cyclic RSD A/D converter , 1992, IEEE Journal of Solid-State Circuits.