Post-Silicon Jitter Measurements

This paper reviews the theory and introduces the architecture for a clock source with low phase noise and for measuring timing jitter. This approach utilizes a sample mean and sum of two random variables, and can be implemented in CMOS or SiGe BiCMOS circuits.

[1]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[2]  Takahiro J. Yamaguchi,et al.  A clock jitter reduction circuit using gated phase blending between self-delayed clock edges , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[3]  Mani Soma,et al.  Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method , 2003 .

[4]  Heinrich Meyr,et al.  Synchronization in digital communications , 1990 .

[5]  Yue Lu,et al.  A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques , 2011, IEEE Journal of Solid-State Circuits.

[6]  Aarnout Brombacher,et al.  Probability... , 2009, Qual. Reliab. Eng. Int..

[7]  Takahiro J. Yamaguchi,et al.  CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation , 2012, IEEE Journal of Solid-State Circuits.

[8]  J. Bendat,et al.  Random Data: Analysis and Measurement Procedures , 1987 .

[9]  K. Ichiyama,et al.  A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  Kunihiro Asada,et al.  A New Procedure for Measuring High-Accuracy Probability Density Functions , 2012, 2012 IEEE 21st Asian Test Symposium.

[11]  John G. Proakis,et al.  Probability, random variables and stochastic processes , 1985, IEEE Trans. Acoust. Speech Signal Process..

[12]  Kamilo Feher,et al.  Telecommunications Measurements, Analysis, and Instrumentation , 1987 .

[13]  Takahiro J. Yamaguchi,et al.  Skew measurements in clock distribution circuits using an analytic signal method , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  E. Klumperink,et al.  Reducing MOSFET 1/f noise and power consumption by switched biasing , 1999, IEEE Journal of Solid-State Circuits.

[15]  Ali M. Niknejad,et al.  A 4-port-inductor-based VCO coupling method for phase noise reduction , 2011, IEEE Custom Integrated Circuits Conference 2010.

[16]  Enrico Monaco,et al.  A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves , 2011, IEEE Journal of Solid-State Circuits.

[17]  Mitsuhiro Shimozawa,et al.  A low noise multi-PFD PLL with timing shift circuit , 2012, 2012 IEEE/MTT-S International Microwave Symposium Digest.