OctaLynx D: RISC microprocessor dedicated for dynamic thermal management

The paper describes features of the OctaLynx RISC microprocessor version dedicated to cooperation with the Dynamic Power Management system with awareness of present circuit temperature. The processor can use two independent interrupts triggered by thermal events. Additional function registers contain information about maximum temperature found in the circuit by the hardware part of the power management system and information to control frequency generated by built-in oscillator. The processor was designed with Verilog hardware description language.

[1]  Chaodong Ling,et al.  A RISC CPU IP core , 2008, 2008 2nd International Conference on Anti-counterfeiting, Security and Identification.

[2]  D. Morris,et al.  Pathlength reduction features in the PA-RISC architecture , 1992, Digest of Papers COMPCON Spring 1992.

[3]  M. Frankiewicz,et al.  Overheat security system for high speed embedded systems , 2012, Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012.

[4]  Andrzej Kos,et al.  ASIC implementation of high efficiency 8-bit 'OctaLynx' RISC microprocessor , 2012 .

[5]  Adam Golda,et al.  FPGA implementation of 8-bit RISC microcontroller for embedded systems , 2011, Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011.

[6]  Rajesh Kannan Megalingam,et al.  Low Power Single Core CPU for a Dual Core Microcontroller , 2010, 2010 3rd International Conference on Emerging Trends in Engineering and Technology.