A fast and area-efficient FPGA-based architecture for high accuracy logarithm approximation

This paper presents a novel hardware architecture for the approximation of the base-2 logarithm of integers at a high accuracy. It is based on a generalized piecewise linear approximation approach, which allows a large number of linear segments to approximate the logarithm function. Contrary to state of the art architectures that utilize up to six linear segments for the approximation, the implementation of the proposed architecture employs up to 1024 linear segments, while retaining low FPGA resource requirements and high frequency. The exploitation of the capabilities of modern FPGAs results in low resource utilization. More specifically, up to 329 slices, one BlockRAM and one multiplier are utilized on a Xilinx Virtex-5 FPGA. The approximation error depends on the number of segments used and is lower than the comparable architectures by five orders of magnitude. Thus, the proposed architecture is suitable for use as a component in systems that require fast, accurate and resource-efficient logarithm calculation.