Pipelined architecture for FPGA implementation of lifting-based DWT

This paper presents a high speed 9/7 lifting 1D-DWT algorithm which is implementation on FPGA with multi-stage pipelining structure. Compared with the architecture which without multi-stage pipeline, the proposed architecture has higher operating frequency, the design raises operating frequency around 1.5 times more fast, at the expense of about 27% more hardware area. The hardware architecture is suitable for high speed implementation.