An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm

The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not.

[1]  Donald R. Jones,et al.  Efficient Global Optimization of Expensive Black-Box Functions , 1998, J. Glob. Optim..

[2]  Paul P. Sotiriadis,et al.  LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Xuan Zeng,et al.  An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  David Pan,et al.  An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization , 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  H. Mostafa,et al.  A Bayesian Optimization Framework for Analog Circuits Optimization , 2020, 2020 15th International Conference on Computer Engineering and Systems (ICCES).

[6]  Yong Wang,et al.  An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Edgar Sanchez-Sinencio,et al.  A 175.2-mW 4-Stage OTA With Wide Load Range (400 pF–12 nF) Using Active Parallel Compensation , 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Farinaz Koushanfar,et al.  Peeking Into the Black Box: A Tutorial on Automated Design Optimization and Parameter Search , 2019, IEEE Solid-State Circuits Magazine.

[9]  Xuan Zeng,et al.  Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Kaushik Roy,et al.  PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[11]  Guoyong Shi,et al.  Symbolic Distortion Analysis of Multistage Amplifiers , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Takashi Nakada,et al.  Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing , 2018, IEEE Micro.

[13]  Xuan Zeng,et al.  An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Xuan Zeng,et al.  Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Baidya Nath Ray,et al.  Synthesis Procedure of Configurable Building Block-Based Linear and Nonlinear Analog Circuits , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Salvador Pinillos Gimenez,et al.  Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Niraj K. Jha,et al.  GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Lars Hedrich,et al.  FEATS: Framework for Explorative Analog Topology Synthesis , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Saraju P. Mohanty,et al.  Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm , 2013, Microelectron. J..

[20]  Mariusz Naumowicz,et al.  Technology migration of analogue CMOS circuits using hooke-jeeves algorithm and genetic algorithms in multi-core CPU systems , 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

[21]  Alex Doboli,et al.  Symbolic Matching and Constraint Generation for Systematic Comparison of Analog Circuits , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Georges G. E. Gielen,et al.  Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Georges G. E. Gielen,et al.  Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model , 2011, 2011 Design, Automation & Test in Europe.

[24]  Chih-Kong Ken Yang,et al.  Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Mourad Loulou,et al.  Analog circuit design optimization through the particle swarm optimization technique , 2010 .

[26]  Zheng Wang,et al.  Analog circuit optimization system based on hybrid evolutionary algorithms , 2009, Integr..

[27]  S. Koziel,et al.  Space Mapping With Multiple Coarse Models for Optimization of Microwave Components , 2008, IEEE Microwave and Wireless Components Letters.

[28]  Gaetano Palumbo,et al.  Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Siegfried Selberherr,et al.  A study on global and local optimization techniques for TCAD analysis tasks , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Sheldon X.-D. Tan,et al.  Efficient approximation of symbolic expressions for analog behavioral modeling and analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Sebastian Magierowski,et al.  CMOS LC-oscillator phase-noise analysis using nonlinear models , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[32]  J.E. Rayas-Sanchez,et al.  EM-based optimization of microwave circuits using artificial neural networks: the state-of-the-art , 2003, IEEE Transactions on Microwave Theory and Techniques.

[33]  Carlos A. Coello Coello,et al.  Use of Particle Swarm Optimization to Design Combinational Logic Circuits , 2003, ICES.

[34]  Jose Silva-Martinez,et al.  A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors , 2003, IEEE J. Solid State Circuits.

[35]  Ranga Vemuri,et al.  Extraction and use of neural network models in automated synthesis of operational amplifiers , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  J. M. Rochelle,et al.  A CAD methodology for optimizing transistor current and sizing in analog CMOS design , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[37]  Georges G. E. Gielen,et al.  Circuit simplification for the symbolic analysis of analogintegrated circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Rob A. Rutenbar,et al.  Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[39]  T.H. Lee,et al.  Oscillator phase noise: a tutorial , 1999, IEEE Journal of Solid-State Circuits.

[40]  Rainer Storn,et al.  Differential Evolution – A Simple and Efficient Heuristic for global Optimization over Continuous Spaces , 1997, J. Glob. Optim..

[41]  Hao Wang,et al.  Introduction to Genetic Algorithms in Electromagnetics , 1995 .

[42]  Boxin Tang.  Orthogonal Array-Based Latin Hypercubes , 1993 .

[43]  Rob A. Rutenbar,et al.  OASYS: a framework for analog circuit synthesis , 1989, Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,.

[44]  Willy Sansen,et al.  Analog Circuit Design Optimization based on Symbolic Simulation and Simulated Annealing , 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference.

[45]  Eric A. Vittoz,et al.  IDAC: an interactive design tool for analog CMOS circuits , 1987 .

[46]  Ching-Yuen Chan,et al.  A particle swarm optimization approach for components placement inspection on printed circuit boards , 2009, J. Intell. Manuf..

[47]  Sushanta K. Mandal,et al.  ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[48]  Xin Li,et al.  Robust Analog/RF Circuit Design With Projection-Based Performance Modeling , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[49]  Vladimir Ceperic,et al.  Modeling of analog circuits by using support vector regression machines , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..