A comparison of second-order sigma-delta modulator between switched-capacitor and switched-current techniques

In this paper, we presents the comparison of second-order sigma-delta modulator (SDM) with switched-capacitor (SC) and switched-current (SI) techniques. In the voltage-mode, we use the switched-capacitor parasitic-insensitive integrator to implement this modulator, but in the current-mode we use sample-and-hold circuit which not only consists of a feedback circuit to reduce the impedance at the input but also with a common-mode feedforward (CMFF) circuit to improve the common-mode offset at the output. The presented second-order sigma-delta modulators simulate with the parameters of the TSMC 0.35 mum CMOS process technology. The simulated results of SC and SI techniques show that the maximum signal-to-noise ratio (SNR) is 89 dB and 86.3 dB, respectively, which are about equal to 14 bits resolution with conditions that the sampling rate is 10.24 MHz, the oversampling ratio is 128, and the consumption is 12 mW.

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