Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-/spl mu/m CMOS

This paper presents the architecture and circuit techniques for a reconfigurable SRAM building block. The memory block can emulate many memory structures including a cache tag or data array, a FIFO, and a simple scratchpad memory. We choose the block size based on the optimal partition size for large SRAM structures, use self-resetting and replica timing circuit techniques, and add flexible status bits and a few hardwired functional blocks to support reconfigurability. A 16-kb prototype design fabricated in a 0.18 /spl mu/m technology cycles at 1.1 GHz at the nominal 1.8 V supply and room temperature. The additional logic used for reconfigurability consumes 32 % of the area and 23 % of the power of the memory block. We project that these overhead percentages would fall below 15% and 10%, respectively, for a 64-kb memory.

[1]  V.G. Oklobdzija,et al.  Sense amplifier-based flip-flop , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach (4. ed.) , 2007 .

[3]  Mircea R. Stan,et al.  5-GHz 32-bit Integer Execution Core in 130-nm Dual-VT CMOS , 2001 .

[4]  Frank Vahid,et al.  A highly configurable cache architecture for embedded systems , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

[5]  S. Hanamura,et al.  A 15-ns 1-Mbit CMOS SRAM , 1988 .

[6]  Ron Ho,et al.  Low-power SRAM design using half-swing pulse-mode techniques , 1998, IEEE J. Solid State Circuits.

[7]  William J. Dally,et al.  Smart Memories: a modular reconfigurable architecture , 2000, ISCA '00.

[8]  Steven A. Guccione,et al.  A Reconfigurable Content Addressable Memory , 2000, IPDPS Workshops.

[9]  Atila Alvandpour,et al.  A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme , 2003 .

[10]  Kathryn Wilcox,et al.  Circuit implementation of a 600 MHz superscalar RISC microprocessor , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[11]  M. Horowitz,et al.  Architecture and circuit techniques for a reconfigurable memory block , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[12]  Rajiv V. Joshi,et al.  A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture , 1991 .

[13]  J. Tschanz,et al.  A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[14]  Noriyuki Suzuki,et al.  A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture , 1992 .

[15]  S. Samaan,et al.  A 0.18 /spl mu/m CMOS IA32 microprocessor with a 4 GHz integer execution unit , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[16]  Bryan D. Ackland,et al.  A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP , 1999 .

[17]  Andrew Leaver,et al.  Programmable memory blocks supporting content-addressable memory , 2000, FPGA '00.

[18]  Bharadwaj Amrutur,et al.  A replica technique for wordline and sense control in low-power SRAM's , 1998, IEEE J. Solid State Circuits.

[19]  David H. Albonesi,et al.  Selective cache ways: on-demand cache resource allocation , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[20]  M.A. Horowitz,et al.  Speed and power scaling of SRAM's , 2000, IEEE Journal of Solid-State Circuits.

[21]  Ron Ho,et al.  Applications of on-chip samplers for test and measurement of integrated circuits , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[22]  M. Horowitz,et al.  Efficient on-chip global interconnects , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[23]  Bharadwaj Amrutur,et al.  Fast low-power decoders for RAMs , 2001, IEEE J. Solid State Circuits.

[24]  M. Usami,et al.  A 1.8 ns access, 550 MHz 4.5 Mb CMOS SRAM , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[25]  Norman P. Jouppi,et al.  Reconfigurable caches and their application to media processing , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[26]  M. Horowitz,et al.  How scaling will change processor architecture , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).