DRAM Yield Analysis and Optimization by a Statistical Design Approach

In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell leakage components or the Gaussian distribution depending on the array structural parameters, parasitic, and the sense amplifier offset voltage. Analytical yield analysis is conducted for several different DRAM architectures and compared to measurements from signal margin analysis and data retention tests. The yield model is found to be very accurate. Thanks to the short computation time, it can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization. It also paves the way for the design for yield of other memory circuits.

[1]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[2]  Masashi Horiguchi,et al.  The impact of data-line interference noise on DRAM scaling , 1988 .

[3]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[4]  K. Hoffmann,et al.  Optimized sensing scheme of DRAMs , 1989 .

[5]  John L. Wyatt,et al.  Mismatch sensitivity of a simultaneously latched CMOS sense amplifier , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[6]  Wentai Liu,et al.  Precise final state determination of mismatched CMOS latches , 1995, IEEE J. Solid State Circuits.

[7]  A. Hiraiwa,et al.  Statistical modeling of dynamic random access memory data retention characteristics , 1996 .

[8]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[9]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[10]  T. Hamamoto,et al.  On the retention time distribution of dynamic random access memory (DRAM) , 1998 .

[11]  Dong-Sun Min,et al.  Multiple twisted dataline techniques for multigigabit DRAMs , 1999, IEEE J. Solid State Circuits.

[12]  Qiuyi Ye,et al.  Signal margin test to identify process sensitivities relevant to DRAM reliability and functionality at low temperatures , 1999, 1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460).

[13]  Sani R. Nassif,et al.  Modeling and analysis of manufacturing variations , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[14]  W. Schwarz,et al.  Statistical analysis of analog structures through variance calculation , 2002 .

[15]  D. G. Laurent.  Sense amplifier signal margins and process sensitivities [DRAM] , 2002 .

[16]  Robert H. Dennard,et al.  Challenges and future directions for the scaling of dynamic random-access memory (DRAM) , 2002, IBM J. Res. Dev..

[17]  Y.J. Park,et al.  Prediction of data retention time distribution of DRAM by physics-based statistical Simulation , 2005, IEEE Transactions on Electron Devices.

[18]  T. Kawahara,et al.  Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM , 2006, IEEE Journal of Solid-State Circuits.

[19]  E. Nowak,et al.  High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .

[20]  Said Hamdioui,et al.  Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Doris Schmitt-Landsiedel,et al.  Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization , 2008, PATMOS.