A power modelling approach for many-core architectures

Many-core architectures are playing an important role in the HPC systems. But they are giving high performance at the cost of a great electrical power consumption. On Tianhe-2 supercomputer, the Xeon Phi many-core processors contribute nearly 80% of the system power. Power models are important to guide the design of dynamic power management (DPM) algorithms by predicting the power consumption with respect to power states and program execution patterns. However, the complexity of many-core hardware design makes power modelling be a challenging work. These concerns lead us to try a power modelling approach for many-core architectures based on the performance monitoring counters (PMC). The key insight is based on a large number of micro benchmarks on a real many-core platform, where we find some essential rules determining the chip power. Following the modelling approach, we develop an accurate chip power model for the Intel SCC many-core chip. Experimental comparison shows that our model is much more accurate than others.

[1]  Saurabh Dighe,et al.  A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling , 2011, IEEE Journal of Solid-State Circuits.

[2]  Lizy Kurian John,et al.  Run-time modeling and estimation of operating system power consumption , 2003, SIGMETRICS '03.

[3]  Christoph W. Kessler,et al.  Modelling Power Consumption of the Intel SCC , 2012, MARC Symposium.

[4]  Shuaiwen Song,et al.  Power, performance and energy models and systems for emergent architectures , 2013 .

[5]  Luca Benini,et al.  Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[6]  Naga K. Govindaraju,et al.  Challenges and Opportunities in Many-Core Computing , 2008, Proceedings of the IEEE.

[7]  W. L. Bircher,et al.  Effective Use of Performance Monitoring Counters for Run-Time Prediction of Power , 2004 .

[8]  Luca Benini,et al.  Single-Chip Cloud Computer thermal model , 2011, 2011 17th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).

[9]  Richard W. Vuduc,et al.  A Roofline Model of Energy , 2013, 2013 IEEE 27th International Symposium on Parallel and Distributed Processing.