An adaptive machine architecture and compiler for dynamic processor reconfigurations

Many computationally intensive tasks spend nearly all of their execution time within a small fraction of the executable code. Substantial gains can be achieved by allowing the configuration and fundamental operations of a processor to adapt to these frequently accessed portions. A method is presented which improves the performance of many computationally intensive tasks by utilizing information extracted at compile-time to synthesize new operations which augment the functionality of a core processor. By integrating adaptation into a general-purpose computer, one not only can reap the performance benefits of application-specific processors, but also retain the general-purpose nature by accommodating a wide variety of tasks. The newly synthesized operations are targeted to RAM-based logic devices which provide a mechanism for fast processor reconfiguration. A proof-of-concept system called PLADO, consisting of a specialized C configuration compiler, and a reconfigurable hardware platform is presented. Compilation and performance results are provided which confirm the concept viability, and demonstrate significant speed-up over conventional general-purpose architectures.