Compact FPGA implementation of Camellia

We present the smallest FPGA implementation of Camellia for 128-bit key length to date. This architecture was designed for low area and low power applications. Through specific optimizations such as shift registers for storing and scheduling key, distributedRAM for storing data, we achieved compact implementation using only 318 slices at a throughput of 18.41Mbps on the smallest Xilinx Spartan-3 XC3S50–5 device.