Dual priority congestion aware shared-resource Network-on-Chip architecture

[1]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[2]  Natalie D. Enright Jerger,et al.  DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[3]  Ming Li,et al.  DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[4]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  An-Yeu Wu,et al.  Spatial-Temporal Enhancement of ACO-Based Selection Schemes for Adaptive Routing in Network-on-Chip Systems , 2014, IEEE Transactions on Parallel and Distributed Systems.

[6]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[7]  Hannu Tenhunen,et al.  Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip , 2013, J. Syst. Archit..

[8]  Huaxi Gu,et al.  A 3D topology based-on partial overlapped clusters for NoC , 2014, IEICE Electron. Express.

[9]  Bevan M. Baas,et al.  Achieving High-Performance On-Chip Networks With Shared-Buffer Routers , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Theocharis Theocharides,et al.  Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Masoud Daneshtalab,et al.  EDXY - A low cost congestion-aware routing algorithm for network-on-chips , 2010, J. Syst. Archit..