Hades-towards the design of an asynchronous superscalar processor

This paper uses Hades, a generic processor architecture aimed at single and multiple-instruction-issue asynchronous implementations, to illustrate some of the difficulties encountered in asynchronous processor design. Particular emphasis is placed on a decoupled operand forwarding mechanism which allows the last result of each functional unit to be forwarded to following instructions, yet completely separates forwarding from the register writeback operation.

[1]  Jim D. Garside,et al.  Register locking in an asynchronous microprocessor , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[2]  Jim D. Garside,et al.  A micropipelined ARM , 1993, VLSI.

[3]  Gurindar S. Sohi,et al.  Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors , 1992, MICRO 1992.

[4]  G. B. Steven,et al.  Using a resource limited instruction scheduler to evaluate the iHARP processor , 1995 .

[5]  Alain J. Martin,et al.  A 100-MIPS GaAs asynchronous microprocessor , 1994, IEEE Design & Test of Computers.

[6]  Gordon B. Steven,et al.  An explicitly declared delayed-branch mechanism for a superscalar architecture , 1994, Microprocess. Microprogramming.

[7]  Ivan E. Sutherland,et al.  The counterflow pipeline processor architecture , 1994, IEEE Design & Test of Computers.

[8]  Steven M. Burns,et al.  The design of an asynchronous microprocessor , 1989, CARN.

[9]  G. B. Steven,et al.  iHARP: a multiple instruction issue processor , 1992 .

[10]  Kemal Ebcioglu,et al.  An efficient resource-constrained global scheduling technique for superscalar and VLIW processors , 1992, MICRO 1992.

[11]  Gordon B. Steven,et al.  ALU design and processor branch architecture , 1993, Microprocess. Microprogramming.

[12]  Edward McLellan The Alpha AXP architecture and 21064 processor , 1993, IEEE Micro.

[13]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.