An ALU-Based BIST Scheme for Word-Organized RAMs

Testing of word-organized memories has been performed in one of these three ways: (1) by repeatedly applying a test for bit-oriented memories using different data backgrounds (which depend on the used intraword fault model), (2) by applying special tests to target intraword faults in addition to applying tests for bit-organized memories, or (3) by applying march tests bit-by-bit to the memory words. The latter solution results in decreased hardware overhead. In this paper, a novel Built-in Self-Test (BIST) scheme is proposed to serially apply march tests bit-by-bit to word-organized RAMs, utilizing an ALU whose inputs are driven by a barrel shifter. Comparisons with schemes that have been proposed in the open literature for the same purpose reveal that the proposed scheme achieves the same fault coverage within the same or lower time and with lower area overhead. More precisely, an overhead of n + 3 gates is required for the application of the required patterns to the RAM inputs and the evaluation of the corresponding outputs, as opposed to the 8n or 11n gates required by schemes proposed previously.

[1]  Dimitris Gizopoulos,et al.  Accumulator-based weighted pattern generation , 2005, 11th IEEE International On-Line Testing Symposium.

[2]  Janusz Rajski,et al.  Arithmetic built-in self-test for DSP cores , 1999 .

[3]  Nicola Nicolici,et al.  Power-constrained embedded memory BIST architecture , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[4]  Jin-Fu Li,et al.  Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test , 2002, J. Electron. Test..

[5]  Constantin Halatsis,et al.  An Accumulator-Based BIST Approach for Two-Pattern Testing , 1999, J. Electron. Test..

[6]  Benoit Nadeau-Dostie,et al.  Serial interfacing for embedded-memory testing , 1990, IEEE Design & Test of Computers.

[7]  Howard Leo Kalter,et al.  Processor-based built-in self-test for embedded DRAM , 1998, IEEE J. Solid State Circuits.

[8]  Kuen-Jong Lee,et al.  An on-chip march pattern generator for testing embedded memory cores , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Ioannis Voyiatzis,et al.  Test vector embedding into accumulator-generated sequences: a linear-time solution , 2005, IEEE Transactions on Computers.

[10]  Janusz Rajski,et al.  Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns , 1996, IEEE Trans. Computers.

[11]  Vinod K. Agarwal,et al.  Fault location algorithms for repairable embedded RAMs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[12]  Wen-Ben Jone,et al.  A parallel built-in self-diagnostic method for embedded memoryarrays , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[14]  Albrecht P. Stroele,et al.  BIST Pattern Generators Using Addition and Subtraction Operations , 1997, J. Electron. Test..

[15]  Jacob Savir.  RAM BIST , 2000, Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference [Cat. No. 00CH37066].

[16]  Fabrizio Lombardi,et al.  A scan-BIST environment for testing embedded memories , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[17]  I. Voyiatzis,et al.  Accumulator - based compression in symmetric transparent RAM BIST , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

[18]  Said Hamdioui,et al.  New data-background sequences and their industrial evaluation for word-oriented random-access memories , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  L. Zakrevski,et al.  BIST for word-oriented DRAM , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[20]  J. Otterstedt,et al.  Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[21]  Benoit Nadeau-Dostie,et al.  A BIST algorithm for bit/group write enable faults in SRAMs , 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

[22]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Ad J. van de Goor,et al.  A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories , 2003, IEEE Trans. Computers.

[24]  Shyue-Kung Lu,et al.  Built-in self-test and repair (BISTR) techniques for embedded RAMs , 2004, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004..

[25]  Katsuhiko Sato,et al.  Universal Test Interface for Embedded-DRAM Testing , 1999, IEEE Des. Test Comput..

[26]  Said Hamdioui,et al.  Opens and Delay Faults in CMOS RAM Address Decoders , 2006, IEEE Transactions on Computers.

[27]  Michael Nicolaidis,et al.  TRANSPARENT BIST FOR RAMS , 1992, Proceedings International Test Conference 1992.

[28]  Janusz Rajski,et al.  Arithmetic Built-In Self-Test for Embedded Systems , 1997 .

[29]  Kuen-Jong Lee,et al.  A high speed BIST architecture for DDR-SDRAM testing , 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

[30]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[31]  Cheng-Wen Wu,et al.  A Programmable BIST Core for Embedded DRAM , 1999, IEEE Des. Test Comput..