Exploring the Performance and Programmability Design Space of Hardware Transactional Memory

In this paper, we study the programmability and performance design space of the new hardware transactional memory (HTM) framework provided by Intel’s Haswell architecture. Towards this, we first present an Intel TSX performance characterization using a simple array access microbenchmark. Through a comprehensive study we identify several important trends, such as, the relationships between, transaction size, write ratio inside transactions, retry count, and transaction abort rate and performance. Next, we explore code transformations such as, computation splitting and privatization, for optimizing the performance of Moldyn, a molecular dynamics simulation from the CHARMM [4] molecular dynamics simulation and analysis package. We leverage our TSX performance characterization to guide and minimize our parametrization efforts for our Moldyn code transformations. We found that a hardware TM solution using computation splitting and privatization can be both easier to program and also outperform a hand-tuned fine-grain pthread locks solution including those same optimizations.