Design of low-leakage and high writable proposed SRAM cell structure

The high demand of embedding more and more functionality in a single chip has enforced the use of scaling. As scaling drastically reduce the channel length the leakage current also increases significantly which increases the static power dissipation. A novel 8T-SRAM cell (Leakage Current Reduced SRAM cell) is proposed which reduces the leakage power dissipation significantly in comparison to the conventional 6T-SRAM cell. The cell is designed using GPDK-90 nm technology library and simulated under Cadence Virtuoso design environment. The proposed cell uses a lower voltage than Vdd during standby mode which leads to a reduction of leakage current and hence the static power consumption. The lower voltage is generated using an NMOS which creates a threshold voltage drop when transfer a high logic. The power consumption is found to be 25.02 % lesser than that of conventional six transistors SRAM cell. The stability and the write ability are measured using the N-Curve technique.