Overstress and electrostatic discharge in CMOS and BCD integrated circuits

Abstract The ESD qualification of the new technologies is obtained by testing different device structures an comparing the ESD robustness evaluated by means of different testing methods (HBM, MM, CDM and TLP). The influence of the layout parameters on the ESD robustness must also be characterized. In this paper we will present data concerning the ESD robustness of both 0.35 μm CMOS and 0.6 μm smart power (BCD5) protection structures. A study of the influence of layout parameters on the ESD robustness with different test methods (HBM, CDM and TLP) will be given. Failure analysis by means of electrical characterization, Emission Microscopy and SEM inspection will also been presented.

[1]  D. Lin.  ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown , 1994 .

[2]  Taylor R. Efland,et al.  Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[3]  Gaudenzio Meneghesso,et al.  HBM and TLP ESD robustness in smart-power protection structures , 1999 .

[4]  G. Notermans,et al.  Pitfalls when correlating TLP, HBM and MM testing , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[5]  Ajith Amerasekera,et al.  ESD in integrated circuits , 1992 .

[6]  Charvaka Duvvury,et al.  A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies , 1999 .

[7]  W. Fichtner,et al.  Characterization and optimization of a bipolar ESD-device by measurements and simulations , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[8]  M. Stecher,et al.  Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[9]  Guido Groeseneken,et al.  NMOS transistor behaviour under CDM stress conditions and relation to other ESD models , 1995 .

[10]  P. Lu,et al.  Collector-base junction avalanche effects in advanced double-poly self-aligned bipolar transistors , 1989 .

[11]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[12]  X. Guggenmos,et al.  Does The Esd-failure Current Obtained By Transmissionline Pulsing Always Correlate To Human Body Model Tests? , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[13]  E. Nowak,et al.  Process and design for ESD robustness in deep submicron CMOS technology , 1996, Proceedings of International Reliability Physics Symposium.

[14]  A. W. Ludikhuize.  Kirk effect limitations in high voltage IC's , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.