Scaling Challenges for the Cross-Point Resistive Memory Array to Sub-10nm Node - An Interconnect Perspective

The impact of Cu interconnect scaling on the write/read margin, energy dissipation, speed and reliability of resistive cross-point memory array are quantitatively examined for wire sizes down to the sub-10nm node. The impending resistivity increase due to wire scaling results in significantly degraded write and read windows, substantial interconnect energy, and increased wire latency. The growing current density required for programming exacerbates the Cu electromigration and is a reliability concern for deeply-scaled technology nodes. Performance degradations are strongly dependent on the memory device parameters and memory array sizes: ron below 100KΩ and array size >; 1Mb lead to write margin <; 55%, read margin <; 5%, and wire energy >; 1pJ for wire size smaller than 20 nm. Also, a large ron value can tolerate a small roff/ron ratio, although a too high ron would result in a slow speed. This work points to the importance of a careful device and interconnect co-optimization to meet the performance specifications for cross- point memory arrays at sub-10nm nodes.