Verilog Netlist Rearrangement Technique in Microwind

Verilog Netlist contains information about the inputs, outputs and interconnects. Microwind is a software tool which is used for CMOS IC layout design. The gate level design is created in schematic editor and simulator tool DSCH. The transistor size in the last few decades is shrinking drastically with the rapid advancement of VLSI technology to integrate more number of transistors on a single IC chip. This will indirectly affect the complexity in the placement and routing of the logic devices. And for any tool it is always a challenging task to make an efficient placement and routing of the cells. One of the EDA tool for CMOS design is MICROWIND, which uses a verilog net list generated by a schematic editor DSCH. This paper focuses on another improvement in Microwind tool by implementing a logic optimization method for rearranging verilog net list according to interconnect wire nodes and number of logic cells like CMOS inverter, NAND, NOR etc. gates using MOS at 120nm technology and using FINFET at 14nm technology. This paper describes the study of rearrangement techniques that can be applied for optimization of CMOS IC layout area, interconnect delay and power dissipation. The main purpose of this paper is to reduce the CMOS IC layout area and power.