System level validation using formal techniques

Owing to increasing design complexity and intensive reuse of components, verifying the correctness of circuits and systems becomes a more and more important factor. In the meantime, in many circuit design projects up to 80% of the overall design costs are caused by verification. By this, checking the correct behaviour becomes the dominating factor. Formal verification has been proposed as a promising alternative to simulation and has become a standard in many flows. In the paper, existing approaches are reviewed and recent trends for system level verification are outlined. To demonstrate the techniques SystemC is used as a system level description language. Besides the successful applications, a list of challenging problems is provided. This gives a better understanding of current problems in hardware verification and shows directions for future research.

[1]  Malay K. Ganai,et al.  Circuit-based Boolean reasoning , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Rolf Drechsler.  Formal Verification of Circuits , 2000, Springer US.

[3]  Rolf Drechsler,et al.  Evolutionary Algorithms for Embedded System Design , 2002, Genetic Algorithms and Evolutionary Computation.

[4]  Bob Bentley,et al.  Validating the Intel(R) Pentium(R) 4 microprocessor , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Rolf Drechsler,et al.  Checkers for SystemC designs , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..

[6]  J. Kukula,et al.  Symbolic RTL simulation , 2001, DAC '01.

[7]  Sharad Malik,et al.  Limits of using signatures for permutation independent Boolean comparison , 1995, ASP-DAC '95.

[8]  Robert K. Brayton,et al.  Using SAT for combinational equivalence checking , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[9]  Robert B. Jones.  Symbolic Simulation Methods for Industrial Formal Verification , 2002 .

[10]  Rolf Drechsler,et al.  Binary decision diagrams in theory and practice , 2001, International Journal on Software Tools for Technology Transfer.

[11]  Bassam Tabbara,et al.  Advanced techniques for RTL debugging , 2003, DAC '03.

[12]  Timothy Kam,et al.  Coverage estimation for symbolic model checking , 1999, DAC '99.

[13]  Dominik Stoffel,et al.  Equivalence checking of arithmetic circuits on the arithmetic bit level , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Edmund M. Clarke,et al.  Sequential circuit verification using symbolic model checking , 1991, DAC '90.

[15]  Jacob A. Abraham,et al.  Abstraction Techniques for Validation Coverage Analysis and Test Generation , 1998, IEEE Trans. Computers.

[16]  Andreas Kuehlmann,et al.  Equivalence checking combining a structural SAT-solver, BDDs, and simulation , 2000, Proceedings 2000 International Conference on Computer Design.

[17]  Rolf Drechsler,et al.  On the relation between SAT and BDDs for equivalence checking , 2002, Proceedings International Symposium on Quality Electronic Design.

[18]  Markus Wedler,et al.  Structural FSM traversal , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Jiang Long,et al.  Smart simulation using collaborative formal and simulation engines , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[20]  Prakash Rashinkar.  System-On-A-Chip verification , 2001 .

[21]  Thomas Kropf,et al.  Introduction to Formal Hardware Verification , 1999, Springer Berlin Heidelberg.

[22]  Janick Bergeron,et al.  Writing Testbenches: Functional Verification of HDL Models, Second Edition , 2003 .

[23]  Wolfgang Rosenstiel,et al.  Simulation-guided property checking based on multi-valued AR-automata , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[24]  Harry Foster,et al.  Principles of verifiable RTL design , 2000 .

[25]  van Caj Koen Eijk,et al.  Formal methods for the verification of digital circuits , 1997 .

[26]  Andreas Kuehlmann,et al.  Equivalence checking using cuts and heaps , 1997, DAC.

[27]  Masahiro Fujita,et al.  Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.