SOC Design Synthesis and Implementation

Most of us know that the ASIC synthesis differs as compare to FPGA synthesis in many ways. When the RTL design phase is over and the initial ASIC synthesis results are available, then the FPGA prototyping phase kicks off. Logic density count during initial synthesis can be used to prototype the single or multiple FPGA designs. In such scenarios, the chapter discusses the synthesis and design implementation for the SOC prototyping. The chapter also discusses the scenarios to get the FPGA equivalent for the ASIC functionality.