Characterization, modeling, and design of ESD protection circuits

iii

[1]  W. Hansch,et al.  The relationship between Oxide charge and device degradation: A comparative study of n- and p- channel MOSFET's , 1987, IEEE Transactions on Electron Devices.

[2]  Sung-Mo Kang,et al.  Electrical overstress (EOS) power profiles: A guideline to qualify EOS hardness of semiconductor devices , 1993 .

[3]  D. Wunsch,et al.  Determination of Threshold Failure Levels of Semiconductor Diodes and Transistors Due to Pulse Voltages , 1968 .

[4]  Theodore I. Kamins,et al.  Device Electronics for Integrated Circuits , 1977 .

[5]  Sung-Mo Kang,et al.  Studies of EOS susceptibility in 0.6 μm nMOS ESD I/O protection structures , 1994 .

[6]  P. Vande Voorde,et al.  Accurate modeling and numerical techniques in simulation of impact-ionization effects on BJT characteristics , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[7]  J. Bruines,et al.  Suppression of soft failures in a submicron CMOS process , 1993 .

[8]  Steven H. Voldman,et al.  Three-dimensional transient electrothermal simulation of electrostatic discharge protection circuits , 1995 .

[9]  Robert W. Dutton,et al.  An automatic biasing scheme for tracing arbitrarily shaped I-V curves , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  R. E. Thomas,et al.  Carrier mobilities in silicon empirically related to doping and field , 1967 .

[11]  J.W. Slotboom,et al.  Surface impact ionization in silicon devices , 1987, 1987 International Electron Devices Meeting.

[12]  G. Simmons,et al.  Snapback Induced Gate Dielectric Breakdown in Graded Junction MOS Structures , 1984, 22nd International Reliability Physics Symposium.

[13]  R. N. Rountree.  ESD protection for submicron CMOS circuits-issues and solutions , 1988, Technical Digest., International Electron Devices Meeting.

[14]  Ajith Amerasekera,et al.  ESD in integrated circuits , 1992 .

[15]  C. Hu,et al.  Lucky-electron model of channel hot-electron injection in MOSFET'S , 1984 .

[16]  Chenming Hu,et al.  Lucky-electron model of channel hot-electron injection in MOSFET'S , 1984, IEEE Transactions on Electron Devices.

[17]  Sung-Mo Kang,et al.  Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  S. G. Beebe.  Methodology for layout design and optimization of ESD protection transistors , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[19]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[21]  Amitava Chatterjee,et al.  Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow , 1992 .

[22]  S. Selberherr.  Analysis and simulation of semiconductor devices , 1984 .

[23]  D. Lin.  ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown , 1994 .

[24]  Amitava Chatterjee,et al.  Hot electron reliability and ESD latent damage , 1988 .

[25]  D. S. Campbell,et al.  Thermal failure in semiconductor devices , 1990 .

[26]  B. Doyle,et al.  Impact of snapback-induced hole injection on gate oxide reliability of N-MOSFETs , 1990, IEEE Electron Device Letters.

[27]  R. V. Overstraeten,et al.  Measurement of the ionization rates in diffused silicon p-n junctions , 1970 .

[28]  C. Duvvury,et al.  Dynamic gate coupling of NMOS for efficient output ESD protection , 1992, 30th Annual Proceedings Reliability Physics 1992.

[29]  John Choma,et al.  Mixed-mode PISCES-SPICE coupled circuit and device solver , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  S. Cristoloveanu,et al.  Two-dimensional modeling of locally damaged short-channel MOSFET's operating in the linear region , 1987, IEEE Transactions on Electron Devices.

[31]  B. S. Doyle,et al.  Examination of oxide damage during high-current stress of n-MOS transistors , 1993 .

[32]  Amitava Chatterjee,et al.  Design and simulation of a 4 kV ESD protection circuit for a 0.8 mu m BiCMOS process , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[33]  C. Duvvury,et al.  Achieving uniform nMOS device power distribution for sub-micron ESD reliability , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[34]  C. Duvvury,et al.  ESD Protection Reliability in 1μM CMOS Technologies , 1986, 24th International Reliability Physics Symposium.

[35]  M.J.O. Strutt,et al.  Secondary breakdown in transistors , 1964 .

[36]  N. Khurana,et al.  ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms , 1985, 23rd International Reliability Physics Symposium.

[37]  C. Hu,et al.  High-current snapback characteristics of MOSFETs , 1990 .

[38]  O. J. McAteer.  Electrostatic damage in hybrid assemblies , 1978 .

[39]  A. Amerasekera,et al.  Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters , 1991 .

[40]  Steven H. Voldman,et al.  Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology , 1994 .

[41]  Guido Groeseneken,et al.  Analysis of HBM ESD testers and specifications using a fourth-order lumped element model , 1994 .

[42]  Massimo Vanzi,et al.  A physically based mobility model for numerical simulation of nonplanar devices , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[43]  Kartikeya Mayaram,et al.  Electrothermal simulation tools for analysis and design of ESD protection devices (NMOSFET) , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[44]  L. Rosenhead.  Conduction of Heat in Solids , 1947, Nature.

[45]  H. Gieser,et al.  Very fast transmission line pulsing of integrated structures and the charged device model , 1998, IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C.

[46]  C. D. Thurmond.  The Standard Thermodynamic Functions for the Formation of Electrons and Holes in Ge, Si, GaAs , and GaP , 1975 .

[47]  Owen J. McAteer.  Electrostatic Discharge Control , 1990 .

[48]  R.W. Dutton,et al.  A computationally stable quasi-empirical compact model for the simulation of MOS breakdown in ESD-protection circuit design , 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

[49]  W. Fichtner,et al.  Layout optimization of an ESD-protection n-MOSFET by simulation and measurement , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[50]  C. Jacoboni,et al.  A review of some charge transport properties of silicon , 1977 .

[51]  C. Duvvury,et al.  Advanced CMOS protection device trigger mechanisms during CDM , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[52]  R. N. Rountree,et al.  Internal chip ESD phenomena beyond the protection circuit , 1988 .

[53]  C. D. Thurmond.  THE STANDARD THERMODYNAMIC FUNCTIONS FOR THE FORMATION OF ELECTRONS AND HOLES IN GE, SI, GAAS, AND GAP , 1975 .

[54]  Sung-Mo Kang,et al.  Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[55]  A. Amerasekera,et al.  Prediction of ESD robustness in a process using 2D device simulations , 1993, 31st Annual Proceedings Reliability Physics 1993.