Towards analyzing functional coverage in SystemC TLM property checking

For Electronic System Level (ESL) design SystemC has become the standard language due to its excellent support of Transaction Level Modeling (TLM). But even if the complexity of the systems can be handled using the abstraction levels offered by TLM - the most abstract one is untimed and focuses on functionality - still verification is the major bottleneck. In particular, as untimed TLM models are the reference for the following refinement steps their correctness has to be ensured. Thus, formal verification approaches have been developed to prove properties for these models. However, even if several properties have been checked this does not guarantee that the complete functionality of the TLM model has been verified. Thus, in this paper we consider the problem of functional coverage analysis in formal TLM property checking. We present a coverage approach which can analyze whether the property set unambiguously describes all transactions in a SystemC TLM model. The developed coverage analysis method identifies uncovered scenarios and hence allows to close all coverage gaps. As an example we consider an automated teller machine and we show the benefits of the proposed approach.

[1]  Rolf Drechsler,et al.  Proving transaction and system-level properties of untimed SystemC TLM designs , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

[2]  Orna Grumberg,et al.  "Have I written enough Properties?" - A Method of Comparison between Specification and Implementation , 1999, CHARME.

[3]  Olivier Ponsini,et al.  Verification of an industrial SystemC/TLM model using LOTOS and CADP , 2009, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design.

[4]  Koen Claessen.  A Coverage Analysis for Safety Property Lists , 2007 .

[5]  Florence Maraninchi,et al.  LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level , 2005, Des. Autom. Embed. Syst..

[6]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[7]  Frank Ghenassia.  Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .

[8]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[9]  Armin Biere,et al.  Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays , 2009, TACAS.

[10]  Rolf Drechsler,et al.  Analyzing Functional Coverage in Bounded Model Checking , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Daniel Kroening,et al.  A Tool for Checking ANSI-C Programs , 2004, TACAS.

[12]  Moshe Y. Vardi,et al.  A Temporal Language for SystemC , 2008, 2008 Formal Methods in Computer-Aided Design.

[13]  Paula Herber,et al.  Model checking SystemC designs using timed automata , 2008, CODES+ISSS '08.

[14]  Franco Fummi,et al.  Properties Incompleteness Evaluation by Functional Verification , 2007, IEEE Transactions on Computers.

[15]  Sven Beyer,et al.  Complete Formal Verification of TriCore2 and Other Processors , 2007 .