Fault-Tolerant Application-Specific Network-on-Chip

The fast scaling in technology has caused the components of a Network-on-Chip (NoC) to be more susceptible to faults; therefore, there is a need for methods to maintain circuit reliability. A fault-tolerant NoC should be able to detect a fault and recover the system to correctly operate the mapped application. In this paper, a fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented which not only is able to recover from single permanent router failure, but also improves the average response time of the system. In this design, a new component, called Link Interface (LI) is also developed to reduce hardware overhead.

[1]  Steve B. Furber.  The Future of Computer Technology and its Implications for the Computer Industry , 2008, Comput. J..

[2]  Vincenzo Catania,et al.  A methodology for design of application specific deadlock-free routing algorithms for NoC systems , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[3]  Radu Marculescu,et al.  Towards on-chip fault-tolerant communication , 2003, ASP-DAC '03.

[4]  Majid Janidarmian,et al.  Application-Specific Networks-on-Chips Design , 2011 .

[5]  Radu Marculescu,et al.  On-Chip Stochastic Communication , 2003, DATE.

[6]  Ahmad Khademzadeh,et al.  Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip , 2009, IEICE Electron. Express.

[7]  An-Yeu Wu,et al.  A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[8]  Anju Vyas.  Print , 2003 .

[9]  Sudeep Pasricha,et al.  NARCO: Neighbor Aware Turn Model-Based Fault Tolerant Routing for NoCs , 2010, IEEE Embedded Systems Letters.

[10]  Ahmad Khademzadeh,et al.  Special Issue on a Fault Tolerant Network on Chip Architecture , 2010, WCE 2010.

[11]  Shekhar Y. Borkar,et al.  Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.

[12]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[13]  Paolo Prinetto,et al.  Reliability in Application Specific Mesh-Based NoC Architectures , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[14]  Pasi Liljeberg,et al.  Multi network interface architectures for fault tolerant Network-on-Chip , 2009, 2009 International Symposium on Signals, Circuits and Systems.

[15]  Ahmad Khademzadeh,et al.  Sorena: New on Chip Network Topology Featuring Efficient Mapping and Simple Deadlock Free Routing Algorithm , 2010, 2010 10th IEEE International Conference on Computer and Information Technology.

[16]  Michael Welzl,et al.  An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip , 2007, Int. J. High Perform. Syst. Archit..

[17]  Ahmad Khademzadeh,et al.  Yield Enhancement with a Novel Method in Design of Application-Specific Networks on Chips , 2011 .

[18]  Luca Benini.  Application Specific NoC Design , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[19]  Zhiyi Yu,et al.  A scalable and fault-tolerant routing algorithm for NoCs , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.