MAHA is a program which implements an algorithm for register level synthesis of data paths from a data flow specification. The algorithm is based on a linear hardware assignment to critical path nodes, followed by a cost-based assignment using the concept of the freedom of a node to be scheduled. Functions with the least scheduling freedom are scheduled first. The program either minimizes cost, subject to a time constraint, or maximizes speed subject to a cost constraint. The implementation of this algorithm is presented using examples from the literature. MAHA is written in Franz LISP, and executes within minutes for problems of practical size on a VAX 11/780.
[1]
D W Knapp,et al.
A Data Structure for VLSI Synthesis and Verification
,
1983
.
[2]
Alice C. Parker,et al.
Synthesis of Hardware for the Control of Digital Systems
,
1982,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3]
Alice C. Parker,et al.
The ADAM Advanced Design Automation System: Overview, Planner and Natural Language Interface
,
1985,
DAC 1985.
[4]
Alice C. Parker,et al.
Synthesis of Optimal Clocking Schemes
,
1985,
DAC 1985.
[5]
Fadi J. Kurdahi,et al.
Area Estimation of VLSI Integrated Circuits.
,
1985
.