Energy-efficient instruction set synthesis for application-specific processors

Several techniques have been proposed to enhance the energy-efficiency of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with a minimal change in the instruction set (IS), they fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this paper, we present an energy-efficient IS synthesis technique that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction count. Experimental results with a typical embedded RISC processor show that our technique can generate application-specific IS's that are up to 40% more energy-efficient over the native IS for several application benchmarks.

[1]  Kurt Keutzer,et al.  A text-compression-based method for code size minimization in embedded systems , 1999, TODE.

[2]  Jihong Kim,et al.  Opcode encoding for low-power instruction fetch , 1999 .

[3]  Luca Benini,et al.  Selective instruction compression for memory energy reduction in embedded systems , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[4]  Donald E. Thomas,et al.  Instruction subsetting: Trading power for programmability , 1998, Proceedings IEEE Computer Society Workshop on VLSI'98 System Level Design (Cat. No.98EX158).

[5]  Kiyoung Choi,et al.  Efficient instruction encoding for automatic instruction set design of configurable ASIPs , 2002, ICCAD 2002.

[6]  Simon Segars.  Low power design techniques for microprocessors , 2000 .

[7]  Kazuaki Murakami,et al.  Reducing power consumption of instruction ROMs by exploiting instruction frequency , 2002, Asia-Pacific Conference on Circuits and Systems.

[8]  Tilman Glökler,et al.  Power efficient semi-automatic instruction encoding for application specific instruction set processors , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[9]  Donald J. Patterson,et al.  Computer organization and design: the hardware-software interface (appendix a , 1993 .

[10]  Donald S. Fussell,et al.  Energy-efficient instruction set architecture for CMOS microprocessors , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[11]  David A. Patterson,et al.  Computer organization and design (2nd ed.): the hardware/software interface , 1997 .

[12]  Luca Benini,et al.  Reducing power consumption of dedicated processors through instruction set encoding , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[13]  R. Govindarajan,et al.  Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).