Utilizing Dark Silicon to Save Energy with Computational Sprinting
暂无分享,去创建一个
Marios C. Papaefthymiou | Thomas F. Wenisch | Milo M. K. Martin | Lei Shao | Arun Raghavan | Laurel Emurian | Kevin P. Pipe | Milo M. K. Martin | T. Wenisch | M. Papaefthymiou | Laurel Emurian | Arun Raghavan | K. Pipe | Lei Shao
[1] Xiaodong Li,et al. Performance directed energy management for main memory and disks , 2004, ASPLOS XI.
[2] Karthikeyan Sankaralingam,et al. Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.
[3] Thomas F. Wenisch,et al. PowerNap: eliminating server idle power , 2009, ASPLOS.
[4] Ragunathan Rajkumar,et al. Critical power slope: understanding the runtime effects of frequency scaling , 2002, ICS '02.
[5] David A. Wood,et al. Cost-Effective Parallel Computing , 1995, Computer.
[6] Marios C. Papaefthymiou,et al. Computational sprinting , 2012, IEEE International Symposium on High-Performance Comp Architecture.
[7] Susanne Albers,et al. Race to idle: New algorithms for speed scaling with a sleep state , 2012, TALG.
[8] Marios C. Papaefthymiou,et al. Computational sprinting on a hardware/software testbed , 2013, ASPLOS '13.
[9] Michael Bedford Taylor,et al. Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse , 2012, DAC Design Automation Conference 2012.
[10] Steven Swanson,et al. Dark Silicon [Guest editors' introduction] , 2013, IEEE Micro.