On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications

Fixed-point accuracy analysis and optimization of polynomial data-flow graphs with respect to a reference model is a challenging task in many digital signal processing applications. Range and precision analysis are two important steps of this process to assign suitable integer and fractional bit-widths to the fixed-point variables and constant coefficients in a design such that no overflow occurs and a given error bound on maximum mismatch (MM) or mean-square-error (MSE) and signal-to-quantization-noise ratio (SQNR) is satisfied. This paper explores efficient optimization algorithms based on robust analyses of MM and MSE/SQNR for fixed-point polynomial data-flow graphs. Experimental results illustrate the robustness of our analyses and the efficiency of the optimization algorithms compared to previous work.

[1]  Emmanuel Boutillon,et al.  Optimizing data flow graphs to minimize hardware implementation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[2]  O. Sarbishei,et al.  Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT) , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[3]  O. Sarbishei,et al.  On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers , 2011, 2011 IEEE 20th Symposium on Computer Arithmetic.

[4]  Chih-Chyau Yang,et al.  Generalized low-error area-efficient fixed-width multipliers , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Robert W. Brodersen,et al.  An Automated Fixed-Point Optimization Tool in MATLAB XSG/SynDSP Environment , 2011 .

[6]  Z. Zhao,et al.  On the generalized DFIIt structure and its state-space realization in digital filter implementation , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Masahiro Fujita,et al.  High-level optimization of integer multipliers over a finite bit-width with verification capabilities , 2009, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design.

[8]  Octavio Nieto-Taladriz García,et al.  Fast and Accurate Computation of the Round-Off Noise of LTI Systems , 2008 .

[9]  W. Luk,et al.  Truncation noise in fixed-point SFGs [digital filters] , 1999 .

[10]  SungWonyong,et al.  Combined word-length optimization and high-level synthesis of digital signal processing systems , 2006 .

[11]  O. Sarbishei,et al.  Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks , 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).

[12]  O. Sarbishei,et al.  Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Jianwen Zhu,et al.  Dynamic-range estimation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Robert W. Brodersen,et al.  Automated fixed-point data-type optimization tool for signal processing and communication systems , 2004, Proceedings. 41st Design Automation Conference, 2004..

[15]  Wayne Luk,et al.  Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems Accuracy Guaranteed Bit-width Optimization Abstract— We Present Minibit, an Automated Static Approach for Optimizing Bit-widths of Fixed-point Feedforward Designs with Guaranteed Accuracy. Methods to Minimize Both the In- , 2022 .

[16]  Vinod Subramaniam,et al.  Digital video broadcasting (DVB); framing structure, channel coding and modulation for digital terr , 2001 .

[17]  E.E. Swartzlander.  Truncated multiplication with approximate rounding , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

[18]  Romuald Rocher,et al.  Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Nicola Nicolici,et al.  Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Katarzyna Radecka,et al.  An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[21]  O. Sarbishei,et al.  Challenges in verifying and optimizing fixed-point arithmetic-intensive designs , 2010, 2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR).

[22]  Pramod Kumar Meher,et al.  A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[23]  Wonyong Sung,et al.  Combined word-length optimization and high-level synthesis ofdigital signal processing systems , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  E. Dubois,et al.  Design of multidimensional finite-wordlength FIR and IIR filters by simulated annealing , 1995 .

[25]  Leland B. Jackson,et al.  On the interaction of roundoff noise and dynamic range in digital filters , 1970, Bell Syst. Tech. J..

[26]  Daniel Ménard,et al.  Automatic evaluation of the accuracy of fixed-point algorithms , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[27]  Joan Carletta,et al.  Determining appropriate precisions for signals in fixed-point IIR filters , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[28]  Wayne Luk,et al.  MiniBit: bit-width optimization via affine arithmetic , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[29]  A. Lipchin,et al.  Multi-operand block-floating point arithmetic for image processing , 2010, 2010 IEEE Workshop On Signal Processing Systems.

[30]  Octavio Nieto-Taladriz,et al.  Fast and accurate computation of the roundoff noise of linear time-invariant systems , 2008, IET Circuits Devices Syst..

[31]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[32]  Masahiro Fujita,et al.  Polynomial datapath optimization using partitioning and compensation heuristics , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[33]  Zeljko Zilic,et al.  Arithmetic transforms for compositions of sequential and imprecise datapaths , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  O. Sarbishei,et al.  Analysis of Mean-Square-Error (MSE) for fixed-point FFT units , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[35]  Wayne Luk,et al.  Wordlength optimization for linear digital signal processing , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Verification of arithmetic datapaths using polynomial function models and congruence solving , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[37]  Norman C. Beaulieu,et al.  A simple polynomial approximation to the gaussian Q-function and its application , 2009, IEEE Communications Letters.

[38]  Andreas Antoniou,et al.  Area-efficient multipliers for digital signal processing applications , 1996 .

[39]  Lan-Da Van,et al.  An efficient systolic architecture for the DLMS adaptive filter and its applications , 2001 .

[40]  George A. Constantinides.  Perturbation analysis for word-length optimization , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[41]  Scott C. Douglas,et al.  A pipelined LMS adaptive FIR filter architecture without adaptation delay , 1998, IEEE Trans. Signal Process..

[42]  Katarzyna Radecka,et al.  Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[43]  Alok N. Choudhary,et al.  Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[44]  John G. Proakis,et al.  Digital Signal Processing: Principles, Algorithms, and Applications , 1992 .

[45]  Rob A. Rutenbar,et al.  Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs , 2003, ICCAD 2003.

[46]  Masahiro Fujita,et al.  Modular Datapath Optimization and Verification Based on Modular-HED , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[47]  Wayne Luk,et al.  Unifying bit-width optimisation for fixed-point and floating-point designs , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[48]  O. Sarbishei,et al.  Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations , 2012, 17th Asia and South Pacific Design Automation Conference.

[49]  Octavio Nieto-Taladriz,et al.  Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[50]  V. J. Mathews,et al.  Polynomial Signal Processing , 2000 .

[51]  Stephen P. Boyd,et al.  Convex Optimization , 2004, Algorithms and Theory of Computation Handbook.

[52]  Romuald Rocher,et al.  Analytical accuracy evaluation of fixed-point systems , 2007, 2007 15th European Signal Processing Conference.

[53]  W. Luk,et al.  Truncation noise in fixed-point SFGs , 1999 .

[54]  Gabriel Caffarena,et al.  SQNR Estimation of Fixed-Point DSP Algorithms , 2010, EURASIP J. Adv. Signal Process..

[55]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[56]  Octavio Nieto-Taladriz,et al.  Bit-width selection for data-path implementations , 1999, Proceedings 12th International Symposium on System Synthesis.

[57]  O. Sarbishei,et al.  Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[58]  Richard M. Jiang,et al.  An Area-Efficient FFT Architecture for OFDM Digital Video Broadcasting , 2007, IEEE Transactions on Consumer Electronics.

[59]  Seehyun Kim,et al.  Fixed-point optimization utility for C and C++ based digital signal processing programs , 1998 .

[60]  Wonyong Sung,et al.  Word-length optimization for high-level synthesis of digital signal processing systems , 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

[61]  Li Lee,et al.  Closed-form and real-time wordlength adaptation , 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).