Abacus - a reconfigurable bit-parallel architecture for early vision

Many important computational problems, including those of computer vision, are characterized by data-parallel, low-precision integer operations on large volumes of data. For such highly structured problems, this thesis develops Abacus, a high-speed reconngurable SIMD (single-instruction, multiple-data) architecture that outperforms conventional microprocessors by over an order of magnitude using the same silicon resources. Earlier SIMD systems computed at relatively slow clock rates compared to their unipro-cessor counterparts. The thesis discusses the problems involved in operating a large SIMD system at high clock rates, including instruction distribution and chip-to-chip communication , presents the solutions adopted by the Abacus design. Although the chip was implemented in a 1989-era VLSI technology, it was designed to contain 1024 processing elements (PEs), operate at 125 MHz, and deliver 2 billion 16-bit arithmetic operations per second (GOPS). The PE and chip architecture are described in detail, as well as the results of testing the chip at 100 MHz. Despite this high performance, the Abacus one-bit ALU is not the optimal point in the design space. An analytical model is developed for performance as a function of ALU width and oo-chip memory bandwidth. Intuition provided by the model leads to the conclusion that an eight-bit ALU is an optimal choice for the current technology. Finally, using the analytical model, area and time parameters from the Abacus chip, and some lessons learned from the chip implementation, a design is presented for a 320 GOPS low-cost single-board system. Abstract Many important computational problems, including those of computer vision, are characterized by data-parallel, low-precision integer operations on large volumes of data. For such highly structured problems, this thesis develops Abacus, a high-speed reconngurable SIMD (single-instruction, multiple-data) architecture that outperforms conventional microprocessors by over an order of magnitude using the same silicon resources. Earlier SIMD systems computed at relatively slow clock rates compared to their unipro-cessor counterparts. The thesis discusses the problems involved in operating a large SIMD system at high clock rates, including instruction distribution and chip-to-chip communication , presents the solutions adopted by the Abacus design. Although the chip was implemented in a 1989-era VLSI technology, it was designed to contain 1024 processing elements (PEs), operate at 125 MHz, and deliver 2 billion 16-bit arithmetic operations per second (GOPS). The PE and chip architecture are described in detail, as well as the results of testing the chip at 100 MHz. Despite this high performance, the Abacus one-bit ALU is not …

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