A 2V low–power CMOS 125Mbaud repeater architecture for UTP5 cables

A repeater has been developed for 125Mbaud twisted pair data communication with binary signal levels. The repeater includes an adaptive equalizer and a driver. This architecture operates from a 2V supply while consuming less than 6mA of current in the equalizer section and 12mA in the driver section. The active die area is less than 0.04mm2in a 0.21 µ digital CMOS process. For 100m UTP5 cable the jitter at the output of the repeater is less than 0.3UI peak to peak (including driver jitter).

[1]  James Parker,et al.  A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet , 1998 .

[2]  J. N. Babanezhad A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[3]  Omid Shoaei,et al.  A CMOS mixed-signal 100 Mb/s receive architecture for fast Ethernet , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).