Low-leakage soft error tolerant port-less configuration memory cells for FPGAs

As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When zeros are stored in the cells, the injected glitch due to particle strike is removed from the stroked node by pull-up or pull-down network of the cells. Thus, our proposed cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes when zeros are stored in the cells. Furthermore, in the proposed cells, when zeros are stored, the sub-threshold leakage current components are reduced by using stacks of transistors in series. These new cells are port-less and the storage nodes of cells are manipulated through the transistors which apply the supply voltages to the cell. Simulation results show that the proposed cells are working correctly during their configuration and idle cycles and that our cells have a lower soft error rate and leakage current in 22-nm, as well as 65-nm technologies.

[1]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[2]  Xuegong Zhou,et al.  Zero-Hardened SRAM Cells to Improve Soft Error Tolerance in FPGA , 2008, 2008 Second International Symposium on Intelligent Information Technology Application.

[3]  Mohammad T. Manzuri Shalmani,et al.  Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications , 2012, Microelectron. J..

[4]  Morteza Saheb Zamani,et al.  Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes , 2011, Microelectron. J..

[5]  Bashir M. Al-Hashimi,et al.  Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  S. Jahinuzzaman,et al.  A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability , 2009, IEEE Transactions on Nuclear Science.

[7]  D. Rossi,et al.  Latch Susceptibility to Transient Faults and New Hardening Approach , 2007, IEEE Transactions on Computers.

[8]  Kaushik Roy,et al.  Leakage in nano-scale technologies: mechanisms, impact and design considerations , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  Wayne Luk,et al.  An Overview of Low-Power Techniques for Field-Programmable Gate Arrays , 2008, 2008 NASA/ESA Conference on Adaptive Hardware and Systems.

[10]  E. Seevinck,et al.  An SRAM array based on a four-transistor CMOS SRAM cell , 2003 .

[11]  Andreas Moshovos,et al.  Low-leakage asymmetric-cell SRAM , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[12]  M. Margala,et al.  Portless SRAM—A High-Performance Alternative to the 6T Methodology , 2007, IEEE Journal of Solid-State Circuits.

[13]  Mehdi Baradaran Tahoori,et al.  Soft error rate estimation and mitigation for SRAM-based FPGAs , 2005, FPGA '05.

[14]  Jason Helge Anderson,et al.  Active leakage power optimization for FPGAs , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  G. Srinivasan,et al.  Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[16]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[17]  Mohammad T. Manzuri Shalmani,et al.  New configuration memory cells for FPGA in nano-scaled CMOS technology , 2011, Microelectron. J..

[18]  R. Guerrieri,et al.  Low leakage techniques for FPGAs , 2006, IEEE Journal of Solid-State Circuits.

[19]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Robert C. Aitken,et al.  Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[21]  Narayanan Vijaykrishnan,et al.  Improving soft-error tolerance of FPGA configuration bits , 2004, ICCAD 2004.

[22]  Yong-Bin Kim,et al.  A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Pankaj Agarwal,et al.  A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[24]  M. Nicolaidis,et al.  Design for soft error mitigation , 2005, IEEE Transactions on Device and Materials Reliability.

[25]  Francis G. Wolff,et al.  Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA , 2007 .

[26]  P. Oldiges,et al.  Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices , 2006, IEEE Transactions on Nuclear Science.

[27]  A.F. Witulski,et al.  Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing , 2008, IEEE Transactions on Device and Materials Reliability.