Optimum Design of FFT Processor with Cascade Structure Based on FPGA

In order to reduce FFT processor with the cascade structure usage amount of buffer memory,a design scheme of the mixed radix 16,radix 2,radix 4 and radix 8 FFT algorithm based on FPGA is introduced.During the realizing of 1024 point FFT processor,using the optimized radix-4FFT to set up radix-16FFT of the cascade structure,and also simple dual-port memory of read and written in the same address,the structure of single-port memory.It can reduce the usage amount of me-mory units dramatically without increasing the sage amount of logical units and guarantee the operational speed.