Exploiting last idle periods of links for network power management
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Mahmut T. Kandemir | Guilin Chen | Mustafa Karaköy | Feihui Li | M. Kandemir | Feihui Li | Mustafa Karaköy | Guilin Chen
[1] William Gropp,et al. Skjellum using mpi: portable parallel programming with the message-passing interface , 1994 .
[2] Sudhakar Yalamanchili,et al. Power constrained design of multiprocessor interconnection networks , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.
[3] David Wentzlaff,et al. Energy characterization of a tiled architecture processor with on-chip networks , 2003, ISLPED '03.
[4] Ken Kennedy,et al. Compiling Fortran D for MIMD distributed-memory machines , 1992, CACM.
[5] William Pugh,et al. Counting solutions to Presburger formulas: how and why , 1994, PLDI '94.
[6] Li-Shiuan Peh,et al. High-level power analysis for on-chip networks , 2004, CASES '04.
[7] Li-Shiuan Peh,et al. Design-space exploration of power-aware on/off interconnection networks , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[8] Niraj K. Jha,et al. A High-level Interconnect Power Model for Design Space Exploration , 2003, ICCAD 2003.
[9] Jaeha Kim,et al. Adaptive supply serial links with sub-1 V operation and per-pin clock recovery , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[10] Li Shang,et al. Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..
[11] Mani B. Srivastava,et al. A survey of techniques for energy efficient on-chip communication , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).