Estimation of partition size for I/sub DDQ/ testing using built-in current sensing

I/sub DDQ/ testing of CMOS circuits can detect faults that are not easily detected using traditional test techniques. The quiescent current drawn by CMOS devices is very small, and certain faults in a device may cause this current to increase by several orders of magnitude. Current sensors are used to detect abnormalities in the quiescent current. The quiescent current in a circuit can be monitored using an external current sensor or a Built-in Current Sensor (BICS). BICS show improvement in speed and resolution over external current sensors. When connecting a BICS to a circuit, the site of the partition, propagation delay and settling time of the circuit must be taken into consideration. Variations in process parameters may cause variations in the fault-free and faulty I/sub DDQ/ in a CMOS device. As the number of gates in a device increase, the distributions of fault-free and faulty I/sub DDQ/ may start to overlap, thus making it impassible to distinguish between fault-free and faulty currents in a device. Adding a BICS to a circuit may increase the settling time of the circuit, due to the lumped capacitance across the BICS. Monte Carlo simulations have been performed on circuits of various sizes and levels to estimate the partition size for I/sub DDQ/ testing using BICS.

[1]  Adit D. Singh,et al.  Incorporating IDDQ testing in BIST: improved coverage through test diversity , 1994, Proceedings of IEEE VLSI Test Symposium.

[2]  Steven D. McEuen.  IDDq benefits (digital CMOS testing) , 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

[3]  Keith Baker,et al.  I/sub DDQ/ testing because 'zero defects isn't enough': a Philips perspective , 1990, Proceedings. International Test Conference 1990.

[4]  Phillip J. Nigh.  Built-in current testing , 1990 .

[5]  Anura P. Jayasumana,et al.  Enhancement of resolution in supply current based testing for large ICs , 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

[6]  Wojciech Maly,et al.  Built-in current testing-feasibility study , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[7]  Roger Perry.  I/sub DDQ/ TESTING IN CMOS DIGITAL ASIC'S - PUTTING IT ALL TOGETHER , 1992, Proceedings International Test Conference 1992.

[8]  Charles F. Hawkins,et al.  Quiescent power supply current measurement for CMOS IC defect detection , 1989 .

[9]  Alan Mathewson,et al.  Relating statistical MOSFET model parameter variabilities to IC manufacturing process fluctuations enabling realistic worst case design , 1994 .

[10]  Mark W. Levi,et al.  CMOS Is Most Testable , 1981, International Test Conference.

[11]  Kozo Kinoshita,et al.  CIRCUIT DESIGN FOR BUILT-IN CURRENT TESTING , 1992, Proceedings International Test Conference 1992.

[12]  Antonio Rubio,et al.  Quiescent current sensor circuits in digital VLSI CMOS testing , 1990 .

[13]  I. M. Sobolʹ.  The Monte Carlo method , 1974 .

[14]  Yashwant K. Malaiya,et al.  Operational and Test Performance in the Presence of Built-in Current Sensors , 1997, VLSI Design.

[15]  Yashwant K. Malaiya,et al.  A New Fault Model and Testing Technique for CMOS Devices , 1982, International Test Conference.

[16]  Wojciech Maly,et al.  Built-in current testing , 1992 .