Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells

This paper presents a march-like testT<sub>AC-P</sub> to cover comparison faults of ternary content addressable memories (TCAMs) with asymmetric cells. The T<sub>AC-P</sub> only requires 4<i>N</i> Write operations and (3<i>N</i>+2<i>B</i>) Compare operations for an <i>N</i> ×<i>B</i> -bit TCAM with Hit and priority address encoder outputs. We show that the test also can cover search time failures induced by process variation in the comparison circuit of a TCAM. Furthermore, a test T<sub>MF</sub> for match failures induced by the process variation in the comparison circuit of a TCAM is also presented.

[1]  Matthias Beck,et al.  Logic design for on-chip test clock generation - implementation details and impact on delay test quality , 2005, Design, Automation and Test in Europe.

[2]  Manoj Sachdev,et al.  Transistor-level fault analysis and test algorithm development for ternary dynamic content addressable memories , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[3]  Narayanan Vijaykrishnan,et al.  Variation Analysis of CAM Cells , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[4]  Sungju Park,et al.  Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains , 2008 .

[5]  Vivek De,et al.  Intrinsic MOSFET parameter fluctuations due to random dopant placement , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Qiang Xu,et al.  Wrapper design for multifrequency IP cores , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Mehrdad Nourani,et al.  Prefix segregation scheme for a TCAM-based IP forwarding engine , 2005, IEEE Micro.

[8]  Yu-Jen Huang,et al.  Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells , 2009, 2009 27th IEEE VLSI Test Symposium.

[9]  Cheng-Wen Wu,et al.  STEAC: A Platform for Automatic SOC Test Integration , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Jin-Fu Li Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Manoj Sachdev,et al.  Design techniques and test methodology for low-power TCAMs , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Jin-Fu Li Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  B.C. Paul,et al.  Process variation in embedded memories: failure analysis and variation aware architecture , 2005, IEEE Journal of Solid-State Circuits.