Reliability challenges in avionics due to silicon aging

Today's aviation systems are strongly dependent on electronics. Avionics (i.e., aviation electronics) should be highly reliable due to the nature of their applications. CMOS technology, which is widely used in the fabrication of integrated circuits, is continuously scaled to achieve higher performance and higher integration density (i.e., the wellknown Moore's law). This scaling property creates new challenges in reliability of avionics. As an example, the aging process is speeded up resulting in shorter time to wear-out. This paper investigates reliability challenges in design of avionics caused by silicon aging. It is shown that in the circuits and systems designed in modern CMOS technology, aging phenomenon have to be considered as a serious concern.

[1]  T. Grasser,et al.  Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices—Application to NBTI , 2010, IEEE Electron Device Letters.

[2]  E. Takeda,et al.  An empirical model for device degradation due to hot-carrier injection , 1983, IEEE Electron Device Letters.

[3]  Saurabh Dighe,et al.  Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.

[5]  Shekhar Y. Borkar,et al.  Electronics beyond nano-scale CMOS , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[6]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[7]  Andrew Holmes-Siedle,et al.  Handbook of Radiation Effects , 1993 .

[8]  Georges G. E. Gielen,et al.  Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[9]  B. Kaczer,et al.  Recent advances in understanding the bias temperature instability , 2010, 2010 International Electron Devices Meeting.

[10]  Rajesh Kumar,et al.  A radiation tolerant Phase Locked Loop design for digital electronics , 2009, 2009 IEEE International Conference on Computer Design.

[11]  David Roy,et al.  Ultra thin gate oxide characterization , 2004 .

[12]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[13]  Gerard Ghibaudo,et al.  Time to breakdown and voltage to breakdown modeling for ultra-thin oxides (Tox<32/spl Aring/) , 2001, 2001 IEEE International Integrated Reliability Workshop. Final Report (Cat. No.01TH8580).

[14]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[15]  T. Grasser,et al.  Evidence That Two Tightly Coupled Mechanisms Are Responsible for Negative Bias Temperature Instability in Oxynitride MOSFETs , 2009, IEEE Transactions on Electron Devices.

[16]  O. Semenov,et al.  CMOS IC technology scaling and its impact on burn-in , 2004, IEEE Transactions on Device and Materials Reliability.

[17]  Guido Groeseneken,et al.  Hot carrier degradation and time-dependent dielectric breakdown in oxides , 1999 .

[18]  N. Vichare,et al.  Prognostics Implementation Methods for Electronics , 2007, 2007 Annual Reliability and Maintainability Symposium.

[19]  B. Agarwala,et al.  Scaling effect on electromigration in on-chip Cu wiring , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[20]  Y. Deval,et al.  A Radiation-Hardened Injection Locked Oscillator Devoted to Radio-Frequency Applications , 2006, IEEE Transactions on Nuclear Science.

[21]  Xiaojun Li,et al.  Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation , 2008, IEEE Transactions on Device and Materials Reliability.

[22]  D. Schroder,et al.  Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing , 2003 .

[23]  Zeng Xu,et al.  NBTI performance enhancement with process integration of High Current Fluorine incorporation and O2 gas asher process in 45nm CMOS technology , 2009, 2009 IEEE International Integrated Reliability Workshop Final Report.

[24]  Chiman Kwan,et al.  An Enhanced Prognostic Model for Intermittent Failures in Digital Electronics , 2007, 2007 IEEE Aerospace Conference.

[25]  Chenming Hu,et al.  Substrate hole current and oxide breakdown , 1986 .

[26]  Subhasish Mitra,et al.  Overcoming Early-Life Failure and Aging for Robust Systems , 2009, IEEE Design & Test of Computers.

[27]  Bo Yang,et al.  Optimized Circuit Failure Prediction for Aging: Practicality and Promise , 2008, 2008 IEEE International Test Conference.

[28]  P. P. Apte,et al.  Modeling ultrathin dielectric breakdown on correlation of charge trap-generation to charge-to-breakdown , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.

[29]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[30]  A. Robinson,et al.  An Embeddable SOI Radiation Sensor , 2009, IEEE Transactions on Nuclear Science.

[31]  K. Olasupo,et al.  Time dependent breakdown of ultrathin gate oxide , 2000 .

[32]  Georges G. E. Gielen,et al.  Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation , 2011, 2011 Design, Automation & Test in Europe.

[33]  P.. Leroux,et al.  Design and Assessment of a Circuit and Layout Level Radiation Hardened CMOS VCSEL Driver , 2007, IEEE Transactions on Nuclear Science.

[34]  Kartik Mohanram,et al.  Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[35]  P.W. Kalgren,et al.  Prognostic health management for avionic systems , 2006, 2006 IEEE Aerospace Conference.

[36]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[37]  Georges Gielen,et al.  Analog IC Reliability Simulation , 2013 .

[38]  Liyi Xiao,et al.  Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[39]  Lap Chan,et al.  Wafer-level electromigration reliability test for deep-submicron interconnect metallization , 1998, Proceedings 1998 Hong Kong Electron Devices Meeting (Cat. No.98TH8368).

[40]  D. L. Goodman Prognostic methodology for deep submicron semiconductor failure modes , 2001 .

[41]  J. W. McPherson,et al.  Field-enhanced Si–Si bond-breakage mechanism for time-dependent dielectric breakdown in thin-film SiO2 dielectrics , 1997 .