Flip chip based on compliant double helix interconnect for high frequency applications

Compliant interconnects are a viable solution for coefficient of thermal expansion (CTE) mismatch failures and it is therefore important to understand their performance at high frequency. In this work, we present double helix shaped compliant interconnects that are designed and fabricated on top of a coplanar waveguide (CPW) test structure followed by flip chip bonding. The high frequency performance of compliant double helix interconnect is simulated and measured. The measured insertion and reflection loss were less than -0.6 dB and -15 dB up to 50 GHz, respectively.

[1]  W. Heinrich,et al.  Theory and measurements of flip-chip interconnects for frequencies up to 100 GHz , 2001 .

[2]  Qi Zhu,et al.  Compliant cantilevered spring interconnects for flip-chip packaging , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[3]  John H. L. Pang,et al.  Thermal cycling analysis of flip-chip solder joint reliability , 2001 .

[4]  Ying Luo,et al.  Microspring Characterization and Flip-Chip Assembly Reliability , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[5]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[6]  Jinlin Wang,et al.  Emerging challenges of underfill for flip chip application , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[7]  Michael C. Hamilton,et al.  Fabrication and Characterization of Double Helix Structures for Compliant and Reworkable Electrical Interconnects , 2014, Journal of Microelectromechanical Systems.

[8]  J. Vlassak,et al.  The mechanical properties of freestanding electroplated Cu thin films , 2006 .

[9]  R. Marcus.  A new coiled microspring contact technology , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[10]  M. C. Hamilton,et al.  Reduced-Loss Ink-Jet Printed Flexible CPW With Copper Coating , 2013, IEEE Microwave and Wireless Components Letters.

[11]  Changqing Liu,et al.  Electrodeposition of indium for bump bonding , 2008, 2008 58th Electronic Components and Technology Conference.

[12]  J. Meindl,et al.  Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration , 2004, IEEE Transactions on Electron Devices.

[13]  B. Dang,et al.  Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics , 2005, IEEE Transactions on Advanced Packaging.

[14]  S. Sitaraman,et al.  G-helix: lithography-based wafer-level compliant chip-to-substrate interconnects , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).