Mitigating DRAM complexities through coordinated scheduling policies

Acknowledgments I wish to thank the multitudes of people who helped me in the lengthy and difficult process of completing a Ph.D. while maintaining my full time position at IBM. That said, working on the industry leading IBM POWER architecture team over this time provided me with many real problems to solve, very much an advantage. This advantage was reciprocated into my work, in that the combined research community provided enumerable solutions. I also thank my advisor Lizy John and our research group LCA. Lizy tolerated the low research productivity periods that correspond with high demands at IBM. She also motivated me to continue, when the end seemed hard to reach. LCA also provided an excellent ecosystem in order to conduct my work. Specifically, LCA member Dimitris Kaseridis was invaluable in both enabling the simulation infrastructure knowhow, combined with his expertise in the field. Members of the IBM team were also a key component in completing this work. The specific members of my development organization contributed to the work include, the full list is too long to name, William Starke, Steve Dodson, Warren Maule, and Balaram Sinharoy. IBM research also proved a tremendous resource. Hillery Hunter's command of memory design and keen insights were exceptionally helpful. In addition v various stages. Most of all I would like to thank my family and friends, who most certainly missed my company as I was spending all my free time down at the ACES building. Contemporary DRAM systems have maintained impressive scaling by managing a careful balance between performance, power, and storage density. In achieving these goals, a significant sacrifice has been made in DRAM's operational complexity. To realize good performance, systems must properly manage the significant number of structural and timing restrictions of the DRAM devices. DRAM's efficient use is further complicated in many-core systems where the memory interface has to be shared among multiple cores/threads competing for memory bandwidth. In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU's data needs, and are mostly oblivious to the main memory. This work demonstrates that the era of many-core architectures has created new main memory bottlenecks, and mandates a new approach: coordination of cache policy with main memory characteristics. vii Using the cache for memory optimization purposes dramatically expands the memory controller's visibility of processor behavior, at …