An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies
暂无分享,去创建一个
[1] Lorenzo Alvisi,et al. Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.
[2] Bin Zhang,et al. FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[3] Lloyd W. Massengill,et al. Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes , 2017, IEEE Transactions on Nuclear Science.
[4] L. W. Massengill,et al. Hardware based empirical model for predicting logic soft error cross-section , 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).
[5] N. Leland,et al. Frequency dependence of soft error rates for sub-micron CMOS technologies , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[6] Trent McConaghy,et al. Variation-Aware Design , 2013 .
[7] Shuming Chen,et al. Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area , 2014, IEEE Transactions on Nuclear Science.
[8] Ming Zhang,et al. A soft error rate analysis (SERA) methodology , 2004, ICCAD 2004.
[9] R.A. Reed,et al. C-CREST Technique for Combinational Logic SET Testing , 2008, IEEE Transactions on Nuclear Science.
[10] G. Wirth,et al. Single Event Transients in Logic Circuits—Load and Propagation Induced Pulse Broadening , 2008, IEEE Transactions on Nuclear Science.
[11] Sujit Dey,et al. A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits , 2004, Proceedings. 41st Design Automation Conference, 2004..
[12] B. L. Bhuva,et al. Reliability-Aware Synthesis of Combinational Logic With Minimal Performance Penalty , 2013, IEEE Transactions on Nuclear Science.
[13] Juan L. Aragón,et al. MASkIt: Soft error rate estimation for combinational circuits , 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).
[14] B. Gilbert,et al. Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST) , 2005, IEEE Transactions on Nuclear Science.
[15] J. S. Kauppila,et al. Effect of threshold voltage implants on single-event error rates of D flip-flops in 28-nm bulk CMOS , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).
[16] L. W. Massengill,et al. Frequency Dependence of Alpha-Particle Induced Soft Error Rates of Flip-Flops in 40-nm CMOS Technology , 2012, IEEE Transactions on Nuclear Science.
[17] H. Asadi,et al. Soft Error Derating Computation in Sequential Circuits , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[18] Sung-Mo Kang,et al. Fast timing simulation of transient faults in digital circuits , 1994, ICCAD.
[19] B. L. Bhuva,et al. Comparison of Combinational and Sequential Error Rates for a Deep Submicron Process , 2011, IEEE Transactions on Nuclear Science.
[20] Abhijit Chatterjee,et al. Soft-error tolerance analysis and optimization of nanometer circuits , 2005, Design, Automation and Test in Europe.
[21] Kartik Mohanram,et al. Simulation of transients caused by single-event upsets in combinational logic , 2005, IEEE International Conference on Test, 2005..
[22] Peter Lidén,et al. A switch-level algorithm for simulation of transients in combinational logic , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[23] Elizabeth M. Rudnick,et al. A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults , 1996, IEEE Trans. Computers.
[24] J. Holmes,et al. A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit , 2009, IEEE Transactions on Nuclear Science.
[25] Nur A. Touba,et al. Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[26] J. S. Kauppila,et al. Estimating Single-Event Logic Cross Sections in Advanced Technologies , 2017, IEEE Transactions on Nuclear Science.