Automatic generation of memory interfaces

With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the interfaces of dedicated memories or memory controllers, slowing down the design space exploration regarding the memory architecture. In order to overcome this drawback, this work extends RTL code generation from ADL models with the automatic generation of memory interfaces. This is accomplished by introducing a new abstract and versatile description format for memory interfaces and their timing protocols.

[1]  Nikil Dutt,et al.  Processor Description Languages , 2008 .

[2]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[3]  Rainer Leupers,et al.  Architecture exploration for embedded processors with LISA , 2002 .

[4]  Rainer Leupers,et al.  Processor/memory co-exploration on multiple abstraction levels , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[5]  Rainer Leupers,et al.  Retargetable Code Generation Based on Structural Processor Description , 1998, Des. Autom. Embed. Syst..

[6]  Srinivas Devadas,et al.  Techniques for accurate performance evaluation in architecture exploration , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Rajat Moona,et al.  High level synthesis from Sim-nML processor models , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[8]  Luca Fanucci,et al.  Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing , 2007, Journal of Real-Time Image Processing.

[9]  Nikil D. Dutt,et al.  Processor-memory coexploration using an architecture description language , 2004, TECS.

[10]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[11]  Gert Goossens,et al.  Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite , 2006, International Symposium on System-on-Chip.

[12]  Rajat Moona,et al.  Processor modeling for hardware software codesign , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[13]  Rainer Leupers,et al.  Optimized ASIP synthesis from architecture description language models , 2007 .

[14]  Nikil D. Dutt,et al.  Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models , 2003, 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings..

[15]  Srinivas Devadas,et al.  ISDL: an instruction set description language for retargetability , 1997, DAC.