High frequency performance of sub-100 nm UTB-FDSOI featuring TiN/HfO2 gate stack

Abstract For the first time, the high frequency (HF) performance of an ultra-thinned body (UTB) fully depleted silicon-on-insulator (FDSOI) incorporating TiN/HfO 2 gate stack is reported. Full small signal equivalent parameters of UTB-FDSOI are extracted and analysed in detailed. It is revealed that UTB-FDSOI with longer unit width W U (same total width W TOT ) results in slightly higher g m that leads to better HF performance. Despite of the mobility degradation due to the quality of the interface between the high- K dielectric and silicon, the measured transition frequency ( f T ) still corresponds well to that predicted from the ITRS roadmap. Optimising the gate stack for low R G is crucial as huge R G in the current technology is the key parameter responsible for the low f MAX obtained. This work can also be considered as the first ever experimental device measured suitable to be used for the Low STand-by Power (LSTP)-based RF/mobile application.

[1]  G. A. Armstrong,et al.  The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance , 2006 .

[2]  B. Jagannathan,et al.  Record RF performance of 45-nm SOI CMOS Technology , 2007, 2007 IEEE International Electron Devices Meeting.

[3]  P. Bai,et al.  A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications , 2006, 2006 International Electron Devices Meeting.

[4]  J. Conner,et al.  Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions , 2003, IEEE Electron Device Letters.

[5]  O. Faynot,et al.  Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack , 2007, 2007 IEEE International Electron Devices Meeting.

[6]  R. Wallace,et al.  High-κ gate dielectrics: Current status and materials properties considerations , 2001 .

[7]  Chenming Hu,et al.  Ultrathin-body SOI MOSFET for deep-sub-tenth micron era , 2000, IEEE Electron Device Letters.

[8]  O. Faynot,et al.  Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm2 6T-SRAM bitcell , 2007, 2007 IEEE International Electron Devices Meeting.

[9]  G. Alastair Armstrong,et al.  Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors , 2005 .

[10]  K. De Meyer,et al.  Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications , 2001 .

[11]  V. Trivedi,et al.  Scaling fully depleted SOI CMOS , 2003 .

[12]  K. F. Lee,et al.  Impact of distributed gate resistance on the performance of MOS devices , 1994 .

[13]  Byung Jin Cho,et al.  Hot-carrier degradation mechanism in narrow- and wide-channel n-MOSFETs with recessed LOCOS isolation structure , 2000 .