VLSI implementation of a sigma-delta bitstream FIR filter

Sigma-delta signal processing or SDSP has been proposed as a method for reducing system costs by eliminating the decoding of a /spl Sigma//spl Delta/ bitstream prior to processing. In this paper we analyse the tradeoff with the more conventional approach through the study of a bitstream FIR filter. We find that the system cost of the SDSP FIR filter is less than that for the decoded PCM filter below a certain number of taps. We also present the design of a VLSI demonstrator chip that implements 16 FIR taps and a remodulator with a 16-bit dynamic range that is cascadable for higher filter orders.

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