Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform
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Nader Bagherzadeh | Jun Ho Bahn | W.-H. Hu | C.-Y. Chen | J. Bahn | N. Bagherzadeh | C.-Y. Chen | Wen-Hsiang Hu
[1] Hideki Imai,et al. Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..
[2] J.P. Derutin,et al. Design of a Scalable Network of Communicating Soft Processors on FPGA , 2007, 2006 International Workshop on Computer Architecture for Machine Perception and Sensing.
[3] Amer Baghdadi,et al. Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.
[4] Amer Baghdadi,et al. Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[5] Norbert Wehn,et al. Network-on-chip-centric approach to interleaving in high throughput channel decoders , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[6] Leonel Sousa,et al. Parallel LDPC Decoding on the Cell/B.E. Processor , 2008, HiPEAC.
[7] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[8] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[9] Gerhard Fettweis,et al. Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[10] Yoon Seok Yang,et al. On Design and Application Mapping of a Network-on-Chip(NoC) Architecture , 2008, Parallel Process. Lett..
[11] Narayanan Vijaykrishnan,et al. Implementing LDPC decoding on network-on-chip , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[12] M. Fiedler. Algebraic connectivity of graphs , 1973 .
[13] Alex Pothen,et al. PARTITIONING SPARSE MATRICES WITH EIGENVECTORS OF GRAPHS* , 1990 .
[14] Ulrike von Luxburg,et al. A tutorial on spectral clustering , 2007, Stat. Comput..
[15] A. J. Blanksby,et al. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder , 2001, IEEE J. Solid State Circuits.
[16] Gerhard Fettweis,et al. A High-Throughput Programmable Decoder for LDPC Convolutional Codes , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).
[17] Michael R. Anderberg,et al. Cluster Analysis for Applications , 1973 .
[18] Wen-Hsiang Hu,et al. Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform , 2009, 2009 21st International Symposium on Computer Architecture and High Performance Computing.
[19] Gene H. Golub,et al. Matrix computations , 1983 .
[20] Frank Kienle,et al. Low Complexity LDPC Code Decoders for Next Generation Standards , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[21] H. Luetkepohl. The Handbook of Matrices , 1996 .
[22] B. Nikolic,et al. Architectures and implementations of low-density parity check decoding algorithms , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..
[23] Leonel Sousa,et al. Massive parallel LDPC decoding on GPU , 2008, PPoPP.
[24] Guido Masera,et al. Implementation of a Flexible LDPC Decoder , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.