This work reports on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and FinFET-based devices using a novel effective work function (EWF) engineering approach which relies on controlled diffusion mechanisms in the gate stack and enables wide VT modulation [>500 mV ΔVT in narrow-fin (WFin≥5 nm), triple-gate FinFETs], with no EOT nor JG penalty, improved mobility and reliability, excellent mismatch performance, up to ~6.3× reduced noise, and minimized parasitic gate resistance. Additionally, we present a thorough evaluation of the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments for planar vs. FinFET devices with different Si crystal orientations, providing a deeper insight into underlying degradation mechanisms. SF6 enables improved mobility and reduced interface trapped charge density (Nit), helping to mitigate the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-EWF metal CMOS scheme suitable for both device architectures. PDA results in substantially improved reliability behavior due to bulk defects reduction.