Completeness-Driven Development
暂无分享,去创建一个
Robert Wille | Rolf Drechsler | Mathias Soeken | Daniel Große | Ulrich Kühne | Julia Seiter | Hoang Minh Le | Melanie Diepenbeck | R. Drechsler | R. Wille | M. Soeken | H. M. Le | Daniel Große | U. Kühne | J. Seiter | Melanie Diepenbeck
[1] Florence Maraninchi,et al. Full simulation coverage for SystemC transaction-level models of systems-on-a-chip , 2009, Formal Methods Syst. Des..
[2] Franco Fummi,et al. Functional qualification of TLM verification , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[3] Ludovic Apvrille,et al. TTool for DIPLODOCUS: an environment for design space exploration , 2008, NOTERE.
[4] Mark van den Brand,et al. Reusable and Correct Endogenous Model Transformations , 2012, ICMT@TOOLS.
[5] Rolf Drechsler,et al. A guiding coverage metric for formal verification , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[6] Rajeev Alur,et al. A Temporal Logic of Nested Calls and Returns , 2004, TACAS.
[7] Brian Bailey,et al. ESL Design and Verification: A Prescription for Electronic System Level Methodology , 2007 .
[8] Koen Claessen. A Coverage Analysis for Safety Property Lists , 2007 .
[9] Orna Kupferman,et al. Coverage Metrics for Temporal Logic Model Checking , 2001, TACAS.
[10] Rolf Drechsler,et al. Analyzing Functional Coverage in Bounded Model Checking , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[11] Moshe Y. Vardi,et al. A Temporal Language for SystemC , 2008, 2008 Formal Methods in Computer-Aided Design.
[12] Daniel Gajski,et al. Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[13] Rolf Drechsler,et al. Towards analyzing functional coverage in SystemC TLM property checking , 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).
[14] Kent L. Beck,et al. Test-driven Development - by example , 2002, The Addison-Wesley signature series.
[15] Perdita Stevens. A Simple Game-Theoretic Approach to Checkonly QVT Relations , 2009, ICMT@TOOLS.
[16] Sven Beyer,et al. Complete Formal Verification of TriCore2 and Other Processors , 2007 .
[17] Daniel Kroening,et al. Coverage in interpolation-based model checking , 2010, Design Automation Conference.
[18] Alper Sen,et al. Concurrency-oriented verification and coverage of system-level designs , 2011, TODE.
[19] Wolfgang Rosenstiel,et al. State-based Analysis and UML-driven Equivalence Checking for C++ State Machines , 2010, FM+AM.
[20] Rolf Drechsler,et al. Proving transaction and system-level properties of untimed SystemC TLM designs , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).
[21] Frank Ghenassia,et al. Transaction Level Modeling with SystemC , 2005 .
[22] Jack Donovan,et al. SystemC: From the Ground Up , 2004 .
[23] Frank Ghenassia. Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems , 2010 .
[24] Wolfgang Rosenstiel,et al. State-based Coverage Analysis and UML-driven Equivalence Checking for C + + State Machines , 2011 .
[25] Rolf Drechsler,et al. Quality-Driven SystemC Design , 2009 .
[26] Brian Bailey,et al. Taxonomy and Definitions for the Electronic System Level , 2007 .