GIT-CERCS Thermal Field Management for Many-core Processors

This paper first presents an analysis of the global thermal field in many core processors in deep nanometer (to 16nm) nodes under power and thermal budget. We show that the thermal field can have significant spatiotemporal non-uniformity along with high maximum temperature. We propose spatiotemporal power multiplexing as a proactive method to reduce spatial and temporal temperature gradients. Several power multiplexing policies are evaluated for a 256 core many-core processor in 16nm nodes which demonstrate that the simple cyclic core-activation can achieve highly uniform thermal field with low maximum temperature.

[1]  Tajana Simunic,et al.  Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Deepak Chandra Sekar,et al.  Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits , 2008 .

[3]  Kevin Skadron,et al.  Many-core design from a thermal perspective , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[4]  David Wentzlaff,et al.  Processor: A 64-Core SoC with Mesh Interconnect , 2010 .

[5]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[6]  Reza Sarvari,et al.  Intsim: a CAD tool for optimization of multilevel interconnect networks , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[7]  José González,et al.  Understanding the Thermal Implications of Multi-Core Architectures , 2007, IEEE Transactions on Parallel and Distributed Systems.

[8]  Saurabh Dighe,et al.  Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  S. Naffziger,et al.  Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[10]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[11]  Pradip Bose,et al.  The case for lifetime reliability-aware microprocessors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[12]  Guoping Xu,et al.  Substantiation of numerical analysis methodology for CPU package with non-uniform heat dissipation and heat sink with simplified fin modeling , 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).

[13]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.